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| SN54/74LS298 QUAD 2-INPUT MULTIPLEXER WITH STORAGE The SN54 / 74LS298 is a Quad 2-Port Register. It is the logical equivalent of a quad 2-input multiplexer followed by a quad 4-bit edge-triggered register. A Common Select input selects between two 4-bit input ports (data sources.) The selected data is transferred to the output register synchronous with the HIGH to LOW transition of the Clock input. The LS298 is fabricated with the Schottky barrier process for high speed and is completely compatible with all Motorola TTL families. QUAD 2-INPUT MULTIPLEXER WITH STORAGE LOW POWER SCHOTTKY * * * * Select From Two Data Sources Fully Edge-Triggered Operation Typical Power Dissipation of 65 mW Input Clamp Diodes Limit High Speed Termination Effects 16 1 J SUFFIX CERAMIC CASE 620-09 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 Qa 15 Qb 14 Qc 13 Qd 12 CP 11 S 10 I0c 9 16 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 N SUFFIX PLASTIC CASE 648-08 16 1 I1b 2 I1a 3 I0a 4 I0b 5 I1c 6 I1d 7 I0d 8 GND 1 D SUFFIX SOIC CASE 751B-03 ORDERING INFORMATION PIN NAMES LOADING (Note a) HIGH S CP I0a - I0d I1a - I1d Qa - Qd Common Select Input Clock (Active LOW Going Edge) Input Data Inputs From Source 0 Data Inputs From Source 1 Register Outputs (Note b) 0.5 U.L. 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.25 U.L. 0.25 U.L. 5 (2.5) U.L. SN54LSXXXJ SN74LSXXXN SN74LSXXXD Ceramic Plastic SOIC LOGIC SYMBOL 3 2 4 1 9 5 76 NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 mA LOW. b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) Temperature Ranges. 10 11 I0a I1a I0b I1b I0c I1c I0d I1d S CP Qa Qb Qc Qd 15 14 13 12 VCC = PIN 16 GND = PIN 8 FAST AND LS TTL DATA 5-1 SN54/74LS298 LOGIC OR BLOCK DIAGRAM I1a 2 I0a 3 I1b 1 I0b 4 I1c 5 I0c 9 I1d 6 I0d 7 S 10 CP 11 R CP S Qa 15 R CP S Qb 14 R CP S Qc 13 R CP S Qd 12 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS Qa Qb Qc Qd FUNCTIONAL DESCRIPTION The LS298 is a high speed Quad 2-Port Register. It selects four bits of data from two sources (ports)under the control of a Common Select Input (S). The selected data is transferred to the 4-bit output register synchronous with the HIGH to LOW transition of the Clock input (CP). The 4-bit output register is fully edge-triggered. The Data inputs (I) and Select input (S) must be stable only one setup time prior to the HIGH to LOW transition of the clock for predictable operation. TRUTH TABLE INPUTS S I I h h I0 I h X X I1 X X I h OUTPUT Q L H L H L = LOW Voltage Level H = HIGH Voltage Level X = Don't Care I = LOW Voltage Level one setup time prior to the HIGH to LOW clock transition. h = HIGH Voltage Level one setup time prior to the HIGH to LOW clock transition. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Supply Voltage Operating Ambient Temperature Range Output Current -- High Output Current -- Low Parameter 54 74 54 74 54, 74 54 74 Min 4.5 4.75 - 55 0 Typ 5.0 5.0 25 25 Max 5.5 5.25 125 70 - 0.4 4.0 8.0 Unit V C mA mA FAST AND LS TTL DATA 5-2 SN54/74LS298 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol S bl VIH VIL VIK VOH Parameter P Input HIGH Voltage 54 Input LOW Voltage 74 Input Clamp Diode Voltage 54 Output HIGH Voltage 74 54, 74 VOL Output LOW Voltage 74 Input HIGH Current 0.1 Input LOW Current Short Circuit Current (Note 1) Power Supply Current - 20 - 0.4 - 100 21 0.35 0.5 20 IIH IIL IOS ICC V A mA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 - 0.65 3.5 0.8 - 1.5 V V Min 2.0 0.7 V Typ Max Unit Ui V Test C di i T Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for p g All Inputs VCC = MIN, IIN = - 18 mA , , VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA IOL = 8.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V VCC = MAX, VIN = 7.0 V VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C, VCC = 5.0 V) Limits Symbol S bl tPLH tPHL Parameter P Propagation Delay, pg y, Clock to Output Min Typ 18 21 Max 27 32 Unit Ui ns ns Test C di i T Conditions VCC = 5.0 V, , CL = 15 pF AC SET-UP REQUIREMENTS (TA = 25C, VCC = 5.0 V) Limits Symbol S bl tW ts ts th th Parameter P Clock Pulse Width Data Setup Time Select Setup Time Data Hold Time Select Hold Time Min 20 15 25 5.0 0 Typ Max Unit Ui ns ns ns ns VCC = 5.0 V 50 Test C di i T Conditions DEFINITIONS OF TERMS SETUP TIME (ts) -- is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) -- is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. FAST AND LS TTL DATA 5-3 SN54/74LS298 AC WAVEFORMS I0 I1* ts(L) CP 1.3 V 1.3 V th(L) tW(L) tW(H) tPLH 1.3 V th(H) ts(H) 1.3 V tPHL S* ts(L) CP 1.3 V th(L) = 0 1.3 V 1.3 V th(H) = 0 ts(H) 1.3 V Q 1.3 V 1.3 V Q Q = I0 Q = I1 *The shaded areas indicate when the input is permitted to *change for predictable output performance. Figure 1 Figure 2 FAST AND LS TTL DATA 5-4 |
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